1. Field of the Invention
This invention pertains to the general field of analog to digital converters. In particular, it provides a new and improved two-step subranging analog to digital converter characterized by a gain matching architecture for all of its constituent elements.
2. Description of the Prior Art
The function of an analog to digital converter (ADC) is to accurately convert an analog input signal, sampled from a varying analog voltage source and held constant for a specified interval of time by sample-and-hold circuitry, into a digital output represented by a coded array of binary bit signals. The output bit information is generated by processing the analog input signal through a number of comparator steps. An n-bit digital output can be produced in one step with 2.sup.n -1 parallel comparators (flash ADC's) or, at the limit, by n sequential steps with a single comparator (successive approximation ADC's). The one step approach obviously provides higher speed of conversion, but is limited by higher input capacitance, power consumption and device yield constraints associated with the high number of comparators in the circuitry.
Thus, in order to partially exploit the benefits of both approaches, designers have developed architectures using one or more low resolution ADC's and a digital to analog converter (DAC) with feedback to build a higher resolution ADC (subranging ADC's). A two-step subranging feedback ADC is one of the most commonly used forms of subranging ADC's and is illustrated in block diagram form in FIG. 1. During the first step, an analog input voltage signal at node 110 from the output of a sample-and-hold amplifier (not shown) is fed into an m-bit low-resolution flash ADC 130 through a switch 128 in a subtractor and error amplifier network 120. The low-resolution flash ADC converts the analog signal into the upper significant m bits of its digital value, which are stored in a logic network 140 and then fed into an m-bit resolution reference DAC 150. The reference DAC reconverts the first step m-bit digital value into an analog value, which is fed back to a subtracting circuit 124 for comparison with the analog input to produce an analog error voltage value. This error voltage is amplified through a differential amplifier 126 and, in the second step of the two-step subranging feedback ADC, fed through the low-resolution flash ADC 130 again to produce the lower significant m bits of the input's digital value. The second step output is then combined with the first step's in the logic network 140 to produce a high resolution digital output 115. The sequencing of the various steps is timed and controlled by appropriate logic circuitry 160.
Theoretically, the use of such a two-step subranging approach makes it possible to produce a digital output with 2m-bit resolution with a single m-bit flash DAC, thus reducing the number of comparators required from 2.sup.2m -1 to 2.sup.m -1. In practice, though, other factors that affect the performance of the two-step subranging converter may reduce its accuracy to unacceptable levels unless specific requirements are met for each of its individual elements. In particular, the reference DAC must have a resolution equal to the low-resolution flash ADC and an accuracy at least equal to the requirements for the overall two-step high-resolution converter. Moreover, the accuracy of the error amplifier must be equal to that of the low-resolution flash ADC. Finally, the gains of the reference DAC, the error amplifier, and the low-resolution flash ADC must track with an accuracy at least as great as that of the low-resolution flash ADC. While proper design and selection of components have been used to meet the resolution and accuracy specifications, these gain matching requirements have continued to be an obstacle to the optimal utilization of two-step subranging analog-to-digital conversion.
Various types of subranging ADC's are described in several U.S. Pat., such as No. 4,612,531 to Dingwall et al. (1986); U.S. Pat. No. 4,804,960 and U.S. Pat. No. 4,814,767 to Fernandes et al. (1989); and U.S. Pat. No. 4,816,831 to Mizoguchi et al. (1989). In particular, in U.S. Pat. No. 4,875,048 (1989), Shimizu et al. disclose a two-step parallel ADC with gain matching requirements typical of subranging ADC's. They provide a gain correction circuit that automatically establishes a gain for the reference DAC on the basis of a reference voltage applied to a first low-resolution flash ADC used to generate the upper significant bits of the digital output. In addition, a separate reference-voltage generating circuit is provided to establish the upper and lower reference voltages, on the basis of the step voltage of the reference DAC, of a second low-resolution flash ADC used to generate the lower significant bits of the digital output. The circuitry described involves the use of control amplifier loops to force the various gains to track.
The prior art does not disclose a subranging ADC where the gain matching of the various components is obtained by a special architecture of the ADC itself, without the use of additional circuitry dedicated to that purpose. In fact, most of the prior art implemented into commercial products consists of 10-bit resolution subranging ADC's that either accept the nonlinearity resulting from lack of gain tracking or correct it by means of additional control circuitry. Thus, there still exists a need for a multi-step subranging ADC architecture that by itself provides the required gain tracking characteristics with a minimum number of components and low complexity for high speed, good accuracy, low power consumption, and low cost implementation.